Introduction, CAD Tool flows, Custom VLSI and Cell Design Flow, Hierarchical Cell, Tool Setup and Execution Scripts, Typographical Conventions, Cadence DFII and ICF, Cadence Design and Framework, Starting Cadence, Composer Schematic Capture and creating New Working Library and new cell; creating the Schematic View of a Full Adder and symbol. Creating a Two-Bit adder using the Full Adder; Schematics the use Transistors; Printing Schematics and Modifying PostScript; Plot Files, Pin, and Cell Naming Verilog Simulation; Verilog Simulation of Composer Schematics; NC Verilog: Simulating a Schematic Behavioral Verilog Code in Composer; Generating a Behavioral View; Stand-alone Verilog Simulation, Timing in Verilog Simulations, Transistors Timing, Virtuoso layout Editor; Design rule checking Standard Cell Design Template; Spectrum Analog Simulator, Cell Characterization, Verilog Synthesis; Abstract Generation, Encounter GUI; Chip Assembly, Design Practice.